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| Datasheet File OCR Text: |
| NJW1106 PPRELIMINARY DOLBY PRO LOGIC SURROUND DECODER n GENERAL DESCRIPTION The NJW1106 is a surround processor including all of the necessary circuits of Dolby Pro Logic Surround decoder and digital delay. 2 All of internal statuses are controlled by I C BUS interface. In addition to Dolby Pro Logic Surround function, it performs easily other surround function such as Hall, Live, Disco and others. n PACKAGE OUTLINE NJW1106FC2-80 NJW1106FC2 Dolby and double-D symbol are trademarks of Dolby Laboratories Licensing Corporation. San Francisco, CA94103-4813.USA. This device is available only to licensees of Dolby Lab. Licensing and application information may be obtained from Dolby Lab. Purchase of I2C components of New Japan Radio Co., Ltd. or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. n FEATURES l Operating Voltage : VCC=10V(Analog Block), VDD=5V(Digital Block) l Digital Delay on chip 2 l I C BUS Interface SDA, SCL l Bi-CMOS Technology l Package Outline QFP80, QFP100 n FUNCTION [Dolby Pro Logic Surround] l Automatic input balance l Noise sequencer l Adaptive matrix l Center channel control (Wide, Normal, Phantom, Off) l Modified B-type noise reduction l 7kHz low-pass filter l Dolby 3 stereo mode l Digital time delay (15,20,25,30msec.) n SYSTEM BLOCK DIAGRAM [Other Surround] l Surround Signal Selector (L+R, L-R, EXTIN) l Front mixing control l Digital time delay (15,20,25,30,40,50,60msec.) [Other Function] l Digital auxiliary outputs (AUX0-AUX7) LIN RIN Input Autobalance Noise Sequencer Adaptive Matrix Center Mode LOUT COUT ROUT Modified BNR 7KHz LPF L+R L-R EXTIN Delay SOUT I2C Interface SW. Controller ADD/SUB SDA SCL AUX0-7 MD1 MD2 Ver.1.0 -1- NJW1106 n ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER Supply Voltage Power Dissipationo Operating Temperature Range Storage Temperature Range SYMBOL VCC VDD PD Topr Tstg RATING 13 6.5 (QFP80) 1.3 (QFP100) 1.3 -40 to +85 -40 to +150 UNIT V W C C *On board n ELECTRICAL CHARACTERISTICS (VCC=10V, VDD=5V, Ta=25C) PARAMETER OVERALL X Supply Voltage Range Supply Current Reference Voltage Threshold Voltage INPUT AUTO BALANCE X Capture Range Error Correction Output Level Accuracy relative to Cch Matrix Rejection relative Headroom Total Harmonic Distortion Signal to Noise Ratio NOISE SEQUENCER X Output Noise Level Output Noise Level Accuracy relative to Cch MODIFIED B-TYPE NOISE REDUCTION (0dB=300mVrms, f=100Hz at Sin Sout) X Voltage Gain Decode Responce1 Decode Responce2 Decode Responce3 Decode Responce4 Total Harmonic Distortion Headroom Signal to Noise Ratio GV-NR DEC1 DEC2 DEC3 DEC4 THDNR HRNR SNNR Vin=0dBd,f=100Hz Vin=0dBd,f=1kHz Vin=-15dBd,f=1.4kHz Vin=-20dBd,f=1.4kHz Vin=-40dBd,f=5kHz Vin=0dBd,f=1kHz VCC=9V at THD=1% Rg=0,weightted:CCIR/ARM -1.6 -3.0 -4.9 -6.8 15 73 9.5 -0.1 -1.5 -3.4 -5.3 0.07 17 78 1.4 0.0 -1.9 -3.8 0.3 dB dB dB dB dB % dB dB Vno 'Vno L,R,S'ch.out -15.0 -0.5 -12.5 0.0 -10.0 0.5 dB dB MR HR-AM THD-AM SNAM L,R,S'ch.out VCC=9V at THD=1% L,R,C,S'ch.out at 4ch.mode L,R,ch.out at 2ch.mode Rg=0,wt:CCIR-ARM at 4ch.mode L,R,ch.out at 2ch.mode 25 15 75 93 40 17 0.05 0.002 80 100 0.2 0.1 dB dB % % dB dB CPR CER 'Vol L,R,S'ch.out -0.5 5 4 0 0.5 dB VCC VDD ICC IDD VREF Vthh Vthl No Signal No Signal No Signal Digital input high level Digital input low level 9 4.5 3.6 0.7VDD 0.0 10 5 37 6 4.0 13 5.5 50 10 4.4 VDD 0.3VDD V V mA mA V V V SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT ADAPTIVE MATRIX (0dB=300mVrms, f=1kHz at Cin Cout) X Ver.1.0 -2- NJW1106 n ELECTRICAL CHARACTERISTICS (VCC=10V, VDD=5V, Ta=25C) PARAMETER OTHER SURROUND X Total Harmonic Distortion Headroom Signal to Noise Ratio DIGITAL TIME DELAY X Delay Time Td fOSC=4MHz 12.4 17.5 22.6 27.7 38.0 48.2 58.4 Total Gain Total Harmonic Distortion Gv THD Vin=0.3Vrms f=1kHz 30kHz LPF Td=15.4ms Td=20.5ms Td=25.6ms Td=30.7ms Td=41.0ms Td=51.2ms Td=61.4ms Maximum Output Voltage Output Noise Voltage Vomax No Vin:f=1kHz 30kHz LPF,THD=3% Rg=600: Vin=0Vrms JIS-A Td=15.4ms Td=20.5ms Td=25.6ms Td=30.7ms Td=41.0ms Td=51.2ms Td=61.4ms DIGITAL AUXILIARY OUTPUT X Low Level Output High Level Output VOL VOH Output Current=-1mA Output Current=1mA 0.0 0.7VDD 0.3V DD VDD dB dB -85 -85 -85 -80 -80 -80 -75 -75 -75 -75 -70 -70 -70 -65 dBV dBV dBV dBV dBV dBV dBV -3.0 1.5 15.4 20.5 25.6 30.7 41.0 51.2 61.4 0.0 0.3 0.3 0.4 0.5 0.6 0.7 0.8 1.8 18.4 23.5 28.6 33.7 44.0 54.2 64.4 3.0 0.6 0.6 0.8 1.0 1.2 1.4 1.6 ms ms ms ms ms ms ms dB % % % % % % % Vrms THDOS HROS SNOS Vin=0dBd,f=1kHz L+R,L-R output VCC=9V at THD=1% L+R,L-R mode Rg=0,weighted:CCIR/ARM L+R,L-R mode 75 80 dB 15 17 dB 0.05 0.2 dB SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Ver.1.0 -3- NJW1106 n PACKAGE OUTLINE (QFP100-C2) 0 - 10 23.9 0.3 20.0 0.4 80 51 81 50 0.3 14.0 100 31 3.0MAX 0.1 0.15 0.15 n PIN CONNECTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name RLC3 RLC8 RLC6 LLI LBPF RLI RBPF LT RT LIN RIN HOLDC NGC3 NGC2 NGC1 GND MD1 MD2 VSS NC NC NC NC NC NC Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name NC NC NC NC NC VSS SM0 SM1 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 RST NC SDA SCL NC CLK2 CLK1 VDD NC Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name NC NC NC NC NC NC NC NC NC NC NC VDD VCC SDOUT LPF1IN LPF1OUT OPA1IN OPA1OUT CC1 CC2 OPA2IN OPA2OUT LPF2IN LPF2OUT LPFIN Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name DBIN DBC1 DBC2 DBC3 LOUT ROUT COUT SOUT CMC SMRO SMRI EXTIN VREF IREF PSC3 PSC6 PSC2 PSC5 PSC1 PSC4 RLC5 RLC2 RLC1 RLC4 RLC7 Ver.1.0 -4- 0.1 0.8 0.1 0.1 2.7 0.65 0.30 0.1 0.12 M 0.1 1 30 17.9 0.4 NJW1106 n PACKAGE OUTLINE (QFP80-C2) 0 - 10 23.9 0.3 20.0 0.4 64 41 65 40 80 25 3.0MAX 0.1 0.15 0.15 n PIN CONNECTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name MD2 MD2 VSS SM0 SM1 AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0 RST NC SDA SCL NC CLK2 CLK1 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name NC VDD VCC VCC SDOUT SDOUT LPF1IN LPF1OUT OP1IN OP1OUT CC1 CC2 OP2IN OP2OUT LPF2IN LPF2OUT LPFIN DBIN DBC1 DBC2 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin Name DBC3 LOUT ROUT COUT SOUT CMC SMRO SMRI EXTIN VREF IREF PSC3 PSC6 PSC2 PSC5 PSC1 PSC4 RLC5 RLC2 RLC1 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Name RLC4 RLC7 RLC3 RLC8 RLC6 LLI LBPF RLI RBPF LT RT LIN RIN HOLDC NGC3 NGC2 NGC1 GND MD1 MD1 0.1 0.8 0.1 0.1 2.7 0.8 0.35 0.1 0.12 M 0.1 1 24 14.0 0.4 17.9 0.3 Ver.1.0 -5- NJW1106 MEMO [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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